As integration of elements in integrated circuits (IC) increases, line widths and geometries for semiconductor devices are reduced. Accordingly, resistance of a gate and source/drain regions of a MOS transistor made by conventional techniques is relatively high. To reduce the resistance, a metal silicide layer is formed on the gate or the source/drain regions by a self-aligned silicide (salicide) process, and then an interlayer dielectric (ILD) layer is formed on the metal silicide layer for isolation. Thereafter, the ILD layer is etched using an etchant to form a trench to expose a metal silicide layer, such that a contact plug may be formed on the metal silicide layer and extends to a surface of the ILD layer through the trench. At operation of forming the trench, the metal silicide layer is often damaged by the etchant. In some conditions, the metal silicide layer is even penetrated, and the subsequently formed contact plug is electrically connected to the gate or the source/drain regions directly, and thus the effect of the metal silicide layer reducing the resistance of the gate and source/drain regions of the MOS transistor is decreased or fails. Therefore, the purpose of reducing the resistance using the metal silicide layer cannot be fully achieved.